A latch is used to store data bits to be written into pre-selected memory cells of a non-volatile memory. Except when data bits are being written into the memory cells, the latch is normally supplied with a low-voltage power supply, such as, for example, 3 volts or less. During a write mode of operation, the latch is supplied with a high voltage of 7-15 volts, as required for writing data into the non-volatile memory cells. A single non-volatile memory chip may contain a large number, for example, 512 or more, of high-voltage latch circuits. These latch circuits are typically called high-voltage latch circuits, although a high voltage supply is only required for write operations. An on-chip high-voltage supply or generator, such as a charge pump circuit, provides the high-voltage for writing the data bits into the non-volatile memory cells. The high-voltage generator typically has limited current capability and excessive leakage currents in some of the high-voltage latches may load down the generator so much as to cause the high-voltage level to be less than what is required for proper writing of data bits into the memory cells of the non-volatile memory.
FIG. 1 illustrates a typical cross-coupled high-voltage latch circuit 10 that includes a first CMOS inverter circuit 12 and a second CMOS inverter circuit 14. The first CMOS inverter circuit 12 includes a first pull-up PMOS transistor 16 that has a source connected to a HV node 18 and a drain connected to a latch input node A. The first CMOS inverter circuit 12 also includes a first pull-down NMOS transistor 20 that has a drain connected to the latch input node A and a source connected to ground. The gates of the first pull-up PMOS transistor 16 and the pull-down NMOS transistor 20 are connected together. Note that the HV node 18 is supplied with low voltage except when a write mode of operation occurs.
The second CMOS inverter circuit 14 includes a second pull-up PMOS transistor 22 that has a source connected to the HV node 18 and a drain connected to a data storage output node B. The second CMOS inverter circuit 14 also includes a second pull-down NMOS transistor 24 that has a drain connected to the data storage output terminal B and a source connected to ground. The gates of the second pull-up PMOS transistor 22 and the second pull-down NMOS transistor 24 are connected together.
To enable operation of the high-voltage latch circuit 10 with a normal low Vdd voltage being supplied at the HV node 18, the second pull-down NMOS transistor 24 is a low-threshold voltage Vt, high-voltage NMOS transistor, which tends to have a high leakage current at high write voltages because of its susceptibility to punch through at high voltages. Thus, a leakage path is provided from the HV node 18 to ground though a leaky second pull-down NMOS transistor 24 with a low threshold voltage, Vt.
A reset NMOS transistor 32 is connected between the latch input node A and ground. A HIGH RESET signal is applied to a RESET terminal 34 to turn on the reset NMOS transistor 32 and pull the latch input node A to ground.
The latch input node A is connected through a load input NMOS transistor 26 to a DATA In terminal 28. A LOAD signal is provided at a gate terminal 30 of the load input NMOS transistor 26 to load a data bit at the DATA IN terminal 28 into the latch input node A.
An OUTPUT terminal 36 provides the signal from the latch input node A that is provided to write to the memory.
When the non-volatile chip is not being used in a high-voltage write mode of operation, a Vdd logic-circuit power supply voltage of 3 volts, for example, is provided to the HV node 18 to power the two inverters 12, 14 forming the high-voltage latch 10. When the non-volatile chip is actually being used in a high-voltage write mode of operation, a suitable high-voltage power supply of, for example, 7-15 volts is provided to the HV node 18 to power the two inverters 12, 14 forming the high-voltage latch. The high-voltage is supplied from a high-voltage generation circuit, such as, for example, a charge-pump circuit that is provided on the chip.
In order to provide for proper switching operation of the latch with a low Vdd logic-circuit supply voltage, such as, for example, 3 volts or less, the NMOS transistor 24 is a high-voltage, low Vt threshold device. A low VT threshold device is required because it is difficult to load a HIGH or “1” level to the latch because of the Vt voltage drop across the load input NMOS transistor 26 that makes it difficult to load a HIGH or “1” level into the latch input node A.
When the chip is in a high-voltage write mode of operation with the HV terminal 18 at 7-15 volts and when the data storage output node B is at a HIGH, “1”, logic level, the high-voltage pull-up PMOS transistor 22 is turned on and the high-voltage pull-down, low-threshold voltage NMOS transistor 24 is turned off. This essentially places almost all of the 7-15 volts from the HV terminal 18 across the low-threshold NMOS transistor 24. If the high-voltage pull-down NMOS transistor 24 is leaky because of the presence of a punch through path in it, a leakage patch goes from the high voltage at the data storage output node B to ground through the leaky pull-down low-threshold NMOS transistor 24.
A non-volatile memory chip has 512 or more high-voltage latches like the typical high-voltage latch circuit 10, some or all of which may be leaky with a high voltage at their HV voltage supply terminals. Excessive leakage currents taken from the on-chip high voltage generation circuit, such as, for example, an on-chip charge pump, that supplies a nominal 15 volts, may cause the voltage at the HV terminal 18 to be pulled down to, say, 12 volts. The reduced high voltage at the HV terminal 18 may cause malfunctions in a memory write function.
FIG. 2 is a timing diagram that illustrates operation of the typical high-voltage latch circuit 10 of FIG. 1, when the DATA IN signal at the DATA IN terminal 28 is LOW, or at 0 volts. A LOAD signal is initially at a LOW level at the gate terminal 30 of the NMOS load input transistor 26 to keep the NMOS load input NMOS transistor 26 off. Initially, the RESET signal at terminal 34 is HIGH, which turns on the reset NMOS transistor 32 to pull the latch input node A to ground. The HV_ ENABLE signal is initially LOW, which provides a Vdd voltage at terminal 18. When the LOAD signal is raised HIGH to Vdd, the NMOS load input NMOS transistor 26 is turned on to provide a LOW logic level DATA IN signal to the latch input node A and the voltage on the data storage output node B goes HIGH to Vdd. Subsequently, the HV_ENABLE control signal goes high to apply a high voltage HV from a high voltage generation circuit to the HV node 18. The second pull-up PMOS transistor 22 is turned on so that the voltage at the data storage output node B is at essentially the same high voltage as at the HV node 18. The HV voltage at the HV node 18 is initially at a Vdd level. However, after the HV_ENABLE control voltage goes HIGH to connect the high voltage generation circuit to the HV node 18, the HV voltage at node 18 rises to a HV(Actual) level that is less than the full HV(Target) level because of the extra leakage current that the high voltage generation circuit must provide to the leaky pull-down NMOS transistor 24 for a number of such high-voltage latch circuits. The full HV(Target) level is, for example, 15 volts while the HV(Actual) level is, for example, 12 volts due to leakage in various high voltage latch circuits. The voltage at the latch input node A and the OUTPUT terminal 36 remains at a LOW state. The voltage at the data storage node B tracks the HV voltage and only rises to the HV(Actual) level.
FIG. 3 is a timing diagram that illustrates operation of the typical high-voltage latch circuit 10 of FIG. 1, when the DATA IN signal at the DATA IN terminal 28 is HIGH. The LOAD signal is initially at a LOW level at the gate terminal 30 of the NMOS load input transistor 26 to keep the NMOS load input transistor 26 off. Initially, the RESET signal at terminal 34 is HIGH, which turns on the reset NMOS transistor 32 to pull the latch input node A to ground. The HV_ENABLE signal is initially LOW, which provides a Vdd voltage at terminal 18. When the LOAD signal is raised to Vdd, the load input NMOS transistor 26 is turned on to provide a HIGH logic level DATA IN signal to the latch input node A and the voltage on the data storage output node B goes low to 0 volts when the pull-up PMOS transistor 22 is turned off and the pull-down NMOS transistor 24 is turned on. Subsequently, the HV_ENABLE control signal goes high to apply the high voltage HV from a high voltage generation circuit to the HV node 18. The first pull-up PMOS transistor 16 is turned on so that the voltage at the data storage output node B is LOW. The HV voltage at the HV node 18 is initially at the Vdd voltage level. After the HV_ENABLE control voltage goes high to connect the high voltage generation circuit to the HV node 18, the HV voltage at node 18 rises to the full HV(Target) level because there is no leakage current through the pull-down NMOS transistor 24. The signal at latch input node A and the OUTPUT terminal 36 tracks the HV level at the HV terminal 18.
Various possible remedies for reducing the effect of leakage through the pull-down NMOS transistor 24, when the voltage at the data storage output terminal B is at a high-voltage level, have some disadvantages. Changing the process parameters for fabrication of the pull-down NMOS transistor 24 may reduce leakage, but this can cause its threshold voltage Vt to increase and adversely affect low-voltage operation.
To decrease leakage current, the resistance of the pull-down NMOS transistor 24 can be increased by increasing the gate length L of the pull-down NMOS transistor, but this takes more area on the chip and increases the size of the chip. The current output, or strength, of the HV generation circuit can be increased; but this may require a larger pump circuit, which takes more area on the chip and increases the size of the chip. Increasing the strength of the HV generation circuit may also require a high clock frequency to provide a greater write current.
In addition to having leakage current, the typical cross-coupled high-voltage latch circuit 10 has other disadvantages. For low voltage operation, the input signal Vdd-Vt needs to overcome the ground voltage at node A. The inverters for this latch must be sized to avoid contention between the voltage levels for control of the input terminal. To avoid losses for input bitline signals, high voltage devices with low Vt are required not only for loading information into the high voltage latch but also for programming and erasing of the memory itself. Leakage is severe for erase and program operations when a LOW signal is loaded in and a HIGH voltage at the data storage output node B causes leakage through the pull-down NMOS transistor 24. Having larger page sizes makes the current leakage even more severe.